@InProceedings{Tverdyshev:TIME08-164,
  author =       "Sergey Tverdyshev and Eyad Alkassar",
  title =        "Efficient Bit-Level Model Reductions for Automated Hardware Verification",
  booktitle =    "15th International Symposium on Temporal Representation and Reasoning (TIME 2008)",
  pages =        "164--172",
  year =         "2008",
  publisher =    "IEEE Computer Society Press",
  ee =           "http://dx.doi.org/10.1109/TIME.2008.11",
}